During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), microprocessors, and logic devices, several conductive structures are commonly formed. For example, transistor gates and capacitor bottom (storage) and top plates, typically manufactured from doped polysilicon, and interconnects and runners, typically formed from aluminum and/or copper, are formed on various types of devices.
A conductive material which has been used for various semiconductor device structures such as capacitor plates in ferroelectric devices is ruthenium oxide (RuO2). Ruthenium oxide exhibits good step coverage and a uniform thickness across various topographies. However, RuO2 is not stable and is a strong oxidizer. It will, over time, oxidize various metal layers that are in close proximity. For example, if RuO2 is used as a capacitor bottom plate, it will oxidize a titanium nitride or tungsten nitride top plate through a tantalum pentoxide (Ta2O5) capacitor dielectric. Further, a barrier layer must be formed to protect a polysilicon contact pad from the RuO2, as the RuO2 will oxidize the polysilicon and result in a bottom plate being electrically isolated from the contact pad by a silicon dioxide layer.
Attempts have also been made to use ruthenium metal as capacitor plates or as various other structures, as ruthenium metal is stable and is easily planarized during chemical mechanical polishing (CMP). However, methods for forming a ruthenium metal layer, for example using chemical vapor deposition (CVD), result in a layer which has poor step coverage and has a rough surface. Ruthenium metal is formed excessively thin over features with excessive slope changes, and it does not adequately form in narrow areas such as deep digit line contact openings in a manner adequate to maintain its conductive integrity.
A method for forming a uniform ruthenium metal layer across severe topographies and which forms within deep, narrow openings would be desirable.